1. Field of the Invention
The present invention relates to a semiconductor integrated circuit apparatus of a master slice type in which a plurality of basic cells including MOS transistors are regularly arranged. More particularly, the present invention relates to a semiconductor integrated circuit apparatus of a master slice type which is of a CMOS type of BiCMOS type and includes a MOS gate array and a MOS-composite gate array (which constitutes a semiconductor integrated circuit apparatus having a gate array structure in one portion of a semiconductor chip), or a MOS transistor of a P-channel type (which is called a PMOS transistor in the following description) and a MOS transistor of an N-channel type (which is called an NMOS transistor in the following description) in a basic cell. The present invention also relates to a method for manufacturing the semiconductor integrated circuit apparatus.
2. Description of the Related Art
A field insulating film is used as a first example to separate electric elements from each other in a MOS transistor. In a second example, a turning-off MOS transistor having a gate electrode connected to a power source is used to separate electric elements from each other in a MOS transistor.
For example, basic gates separated from each other by the field insulating film have generally two inputs. Accordingly, when a circuit structure is constructed such that the basic gates have three or five inputs, there are unused gate electrodes so that flexibility with respect to the number of input signals is low.
In an element separating region, it is necessary to dispose a region for connecting a gate electrode to power source wiring, thereby reducing wiring efficiency. Further, it is impossible to use this gate electrode in wiring so that the wiring efficiency is further reduced.
A general surge protecting element is constructed by a MOS transistor equal to that constituting an internal logic circuit. Accordingly, no drain withstand voltage of the protecting element is reduced by taking various kinds of measures for securing reliability of the MOS transistor. Therefore, a gate withstand voltage is set to be lower than the drain withstand voltage of the protecting element as a size of the protecting element is reduced. In such a reversing phenomenon, such a protecting element cannot function as a normal protecting element.
In a general diode having a PN-junction, a backward withstand voltage depends on temperature so that this diode cannot be used as a constant voltage circuit.
When a logic circuit is constructed by using a general CMOS-type master slice and its logic threshold voltage is changed, it is necessary to dispose plural PMOS and NMOS transistors. Therefore, an area for these MOS transistors is increased on a master slice chip.
Further, the number of used PMOS transistors is not necessarily in conformity with the number of used NMOS transistors. Accordingly, some MOS transistors are unused and the size of a circuit structure is increased.
As mentioned above, each of the PMOS and NMOS transistors included in a basic cell has a constant size. Accordingly, this size is larger than the size of a minimum transistor required to flow a required electric current therethrough so that a direct electric current excessively flows through the MOS transistors.
In a semiconductor integrated circuit apparatus of a master slice type, each of the PMOS and NMOS transistors is set to have an intrinsic channel width. Therefore, if a memory cell is formed in the semiconductor integrated circuit apparatus of a master slice type, the number of used gates is increased and an area for the memory cell is increased.
In another proposed method, a basic unit of the semiconductor integrated circuit apparatus of a master slice type is set by adding PMOS and NMOS transistors and an NMOS transistor of a size smaller than that of each of the PMOS and NMOS transistors to a basic unit cell. When a memory is constructed, the small-sized NMOS transistor is used as an access gate. For example, such a method is shown in "Monthly Semiconductor World" published in February in 1990, pp. 92 to 95. However, in this method, an area for the basic unit cell is increased by adding the small-sized NMOS transistor to this basic unit cell.
In a static RAM, complementary signals on are generally required in a writing operation. To provide a SRAM of high density, there is a method for reducing the number of data lines (bit lines) and the number of MOS transistors by setting each of the complementary signals in the writing operation to a single signal. However, it is necessary to insert an inverter between an access gate and a latch section so as to prevent read data from being fed back to a memory cell. Therefore, it is impossible to provide the SRAM of high density in a semiconductor integrated circuit of a master slice type.
Further, there is another SRAM in which an initial state of the memory cell can be set to prevent this initial state from being undefined when a power source is turned on. The initial state of the memory cell is set by changing operating characteristics thereof as one example of the SRAM. In this example, the size of a MOS transistor constituting the memory cell is changed by changing the width of a diffusive layer of the MOS transistor. The initial state of the memory cell is set by arbitrarily setting the operating characteristics of the memory cell. There is another memory cell for setting the initial state by changing memory cell circuits. For example, such a structure is shown in Japanese Patent Publication (KOKOKU) Nos. 2-30118 and 2-17875.
However, no method for changing the width of the diffusive layer to change the operating characteristics of the memory cell can be applied to the semiconductor integrated circuit apparatus of a master slice type. Further, in the method for changing electric circuits of the memory cell, the electric circuits must be changed in accordance with a set value of the memory cell.